Hi, my name is Abinash Mohanty. I work as a Machine Learning Apps engineer at Annapurna Labs (Amazon AWS). I completed my PhD in Arizona State University, under the guidance of Professor Yu Cao. I am mainly interested in deep learning, especially algorithm design and hardware acceleration. I love travelling and photography (this is my travel blog).

During the course of my career, I have been very fortunate to have a taste of many diverse and fascinating fields. I did my undergraduate studies at National Institute of Technology, Rourkela, India in the field of Electronics and Communications Engineering. After that I had the oppurtunity of working at Samsung Research Institute for 3 wonderful years. My stint at Samsung exposed me to many challenging projects on interesting topics like 3D stereoscopic rendering on embedded platforms, light weight and high performance widget engine using Webkit’s rendering engine etc. I did an internship at Intel Corp in 2016, where I worked on architecture design and implementation of deep learning accelerators for speech processing. I have also worked as consultant for Boehringer Ingelheim and FABU Tech. Did another internship at FABU Tech in summer of 2018. After completing my PhD, worked as a senior design engineer at a startup called FABU Tech, focusing mostly on deep learning algorithms and hardware accelerators for autonomous driving vechiles.

Timeline:

  • 2019-Present: Anapurna Labs (Amazon AWS), Cupertino, CA: Machine Learning Apps Engineer
  • 2018-2019: FABU Tech, Tempe, AZ: Senior Design Engineer
  • Summer 2018: MobAI Tech (currently known as FABU Tech), Tempe, AZ: Deep Learning Research Intern
  • Spring 2018: MobAI Tech (currently known as FABU Tech), Tempe, AZ: Deep Learning Consultant
  • Summer 2017: Boehringer Ingelheim, Germany: Deep Learning Consultant
  • Summer 2016: Intel Corporation, Santa Clara, CA: Graduate Intern
  • 2013-2018: Arizona State Univeristy, AZ: Electrical Engineering PhD. student
  • 2010-2013: Samsung Research Institute, Noida, India: Senior Software Engineer II
  • 2006-2010: National Institute of Technology, Rourkela, India, Electronics & Comm. Engg., BTech

Publications:

  • Mohanty, A., Du, X., Chen, P., Seo, J.S., Yu, S., Cao, Y.,“Random Sparse Adaptation for Accurate Inference with Inaccurate Multi-level RRAM Arrays,” in IEEE International Electron Devices Meeting (IEDM), 2017.
  • Kadambi, P., Mohanty, A., Ren, H., Smith, J., McGuinnes, K., Holt, K., Furtwaengler, A., Slepetys, R., Yang, Zheng., Seo, J.S., Vrudhula, S., Chae, J., Cao, Y., Berisha, V.,“Towards a Wearable Cough Detector based on Deep Neural Networks,” in IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2017, Submitted.
  • Mohanty, A., Suda, N., Kim, M., Vrudhula, S., Seo, J. S., and Cao, Y.,“High-performance Face Detection with CPU-FPGA Acceleration,” in IEEE International Symposium Circuits and Systems (ISCAS), 2016, pp. 117-120.
  • Kim, M., Mohanty, A., Kadetotad, D., Suda, N., Wei, L., Saseendran, P., He, X., Cao, Y. and Seo, J.S., “A Real-time 17-scale Object Detection Accelerator with Adaptive 2000-stage Classication in 65nm CMOS,” in Design Automation Conference (ASP-DAC), 2017 22nd Asia and South Pacific, 2017, pp. 21-22.
  • Suda, N., Chandra, V., Dasika, G., Mohanty, A., Ma, Y., Vrudhula, S., Seo, J.S. and Cao, Y.,“Throughput-optimized OpenCL-based FPGA accelerator for large-scale convolutional neural networks,” in Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2016, pp. 16-25.
  • Mohanty, A., Sutaria, K., Awano, H., Sato, T., and Cao, Y.,“RTN in Scaled Transistors for On-chip Random Seed Generation,” in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2017 Apr 12.
  • Xu, Z., Mohanty, A., Chen, P.Y., Kadetotad, D., Lin, B., Ye, J., Vrudhula, S., Yu, S., Seo, J.S. and Cao, Y.,“Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity,” in BioTL, 2014, pp.126-133.
  • Kadetotad, D., Xu, Z., Mohanty, A., Chen, P.Y., Lin, B., Ye, J., Vrudhula, S., Yu, S., Cao, Y. and Seo, J.S.,“Parallel Architecture with Resistive Crosspoint Array for Dictionary Learning Acceleration,” in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2015, pp.194-204.
  • Chen, P.Y., Kadetotad, D., Xu, Z., Mohanty, A., Lin, B., Ye, J., Vrudhula, S., Seo, J.S., Cao, Y. and Yu, S.,“Technology Design Co-optimization of Resistive Cross-point Array for Accelerating Learning Algorithms on Chip,” in Design, Automation & Test in Europe Conference and Exhibition (DATE), 2015, pp. 854-859.
  • Kadetotad, D., Xu, Z., Mohanty, A., Chen, P.Y., Lin, B., Ye, J., Vrudhula, S., Yu, S., Cao, Y. and Seo, J.S.,“Neurophysics-inspired Parallel Architecture with Resistive Crosspoint Array for Dictionary Learning,” in Biomedical Circuits and Systems Conference (BioCAS), 2014, pp. 536-539.
  • Seo, J.S., Lin, B., Kim, M., Chen, P.Y., Kadetotad, D., Xu, Z., Mohanty, A., Vrudhula, S., Yu, S., Ye, J. and Cao, Y.,“On-chip Sparse Learning Acceleration with CMOS and Resistive Synaptic Devices,” in IEEE Transactions on Nanotechnology (TNANO),2015, pp.969-979.
  • Sutaria, K.B., Mohanty, A., Wang, R., Huang, R. and Cao, Y.,“Accelerated aging in analog and digital circuits with feedback,” in IEEE Transactions on Device and Materials Reliability (TDMR), 2015, pp.384-393.
  • Sutaria, K.B., Ren, P., Mohanty, A., Feng, X., Wang, R., Huang, R. and Cao, Y.,“Duty cycle shift under static/dynamic aging in 28nm HK-MG technology,” in IEEE International Reliability Physics Symposium (IRPS), 2015, pp. CA-7.

My resume can be found here.